As FET (field effect transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance improvements from one successive device generation to the next. Performance may be enhanced by independent optimization of FET device parameters, including those for both p-type and n-type FETs.
Standard components of a FET are the source, the drain, the channel in between the source and the drain, and the gate. The gate overlies the channel and is capable of inducing a current in the channel between the source and the drain. The gate is typically separated from the channel by the gate insulator, or gate dielectric. Depending whether the “on state” current in the channel is carried by electrons or by holes, the FET comes in two kinds: as nFET or pFET. It is also understood that frequently nFET and pFET devices are used together in circuits. Such nFET, pFET combination circuits, known generally as complementary metal oxide semiconductors (CMOS), may find application in analog and digital integrated circuits.
In the fabrication of integrated circuits, one technique that has been found to be advantageous for the pFET device, as well as other FET devices, is to have a channel region formed of a material that exhibits a higher conductivity than pure Si. For example, SiGe may be used as the pFET channel material to enhance electron mobility in the channel. The SiGe channel may be grown using selective epitaxial growth techniques. When using selective epitaxial growth for channel materials on a desired device, a hard-mask material such as silicon dioxide (SiO2) or silicon nitride (Si3N4) may be used to protect against growth of new channel material on other parts of the circuit, such as an nFET device. Growth of the SiGe channel occurs only on crystalline material, not the oxides or nitrides. The hard-mask material is then removed after growth of the SiGe channel is complete.
FIGS. 1-3 illustrate an exemplary fabrication technique currently known in the art for pFET fabrication with a SiGe channel. As shown in FIG. 1, a complementary metal-oxide semiconductor (CMOS) FET circuit is provided that includes a pFET 30, an nFET 35, and a shallow trench isolation (STI) feature 15 between the pFET 30 and the nFET 35. The STI 15, made of a dielectric material such as silicon dioxide, provides electrical isolation between the adjacent semiconductor device components. The nFET 35 includes a hard-mask material 10, such as a hard-mask oxide, to protect the nFET 35 during the growth of channel material on the neighboring pFET 30. Both the pFET 30 and the nFET 35 include an “active” surface 31, 36 respectively, the uppermost surface of the silicon substrate at each respective device at this point in the fabrication process.
At FIG. 2, the native oxide 20 overlaying the pFET 30 (e.g., silicon dioxide) is removed with an oxide etchant, such as hydrofluoric acid (HF), to expose the pFET active surface 31. The oxide etchant also etches a portion of the STI 15 and the hard-mask material 10. At FIG. 3, SiGe is epitaxially grown on the pFET 30 to form a SiGe channel 40. As a result of the growth of the SiGe, however, there is a “step-height” difference 47 between the pFET active surface 31, which is now on top of the SiGe channel 40, and the nFET active surface 36 (shown as distance between parallel dashed lines and shown by double-headed arrow 47). Different size STI divots 45 (amount of STI oxide “pull-down” or height difference immediately next to the pFET SiGe channel 40) may also occur between nFET and pFET devices, due to the formation of the SiGe channel 40 on the Si material only, and not on oxides or nitrides. Step-height differences 47 and divots 45 can create structural topography problems in downstream processing, such as missing high-K material, also known as an encapsulation breach. Encapsulation breaches can result in a lower yielding fabrication process.
As such, there is a need in the art for improved integrated circuit fabrication techniques. Further, there is a need in the art for integrated circuit fabrication techniques that reduce or eliminate the amount and size of step-height differences and divots produced as a result of SiGe channel growth on a pFET. These and other desirable features are provided and will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.